Summary
Proteus Virtual System Modelling (VSM) combines mixed mode SPICE circuit simulation, animated components and microprocessor models to facilitate co-simulation of complete microcontroller based designs.
The ‘Proteus VSM for PIC18’ product includes the following main software modules:
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Proteus VSM for PIC® Bundle products are ideal if you need to simulate more than one family of PIC micro-controllers.
Variants
The following is a current list of supported variants in the PIC18 family:
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Features
We believe our simulation models are the most accurate and the most complete on the market today. A summary of model capabilities is listed below:
- Fully simulates the entire instruction set.
- Supports all port and other I/O pin operations.
- Supports all timers including watchdog timer, sleep mode and wake-up from sleep.
- Supports Deep Sleep mode including independent watchdog timer and wake up from WDT, RTCC, ULPWM, INT0 and MCRL.
- Supports all Capture-Compare-PWM (CCP) modules in all modes and ECCP modules.
- Supports Parallel Slave Port (PSP) module on appropriate devices.
- Supports Parallel Master Port (PMP) module on appropriate devices.
- Supports MSSP in both the SPI mode and the I2C master and slave modes.
- Supports Analogue-to-Digital Conversion (ADC) module inc. support for voltage reference pins.
- Supports Analogue Comparator modules inc. support for internal and external voltage references.
- Supports CTMU, Charge Time Measurement Unit. All modes are simulated.
- Supports ULPWU, Ultra low-power wake-up input.
- Supports REFO, Reference Clock Output.
- Supports RTCC, Real-Time Clock and Calendar.
- Supports SRLatch module.
- Supports DSM, Data Signal Modulator on appropriate devices.
- Supports USART in all modes and EUSART for appropriate variants.
- Supports Universal Serial Bus (USB) on appropriate devices.
- Supports internal code and data EEPROM memory inc. code protection and data persistence.
- Supports Peripheral Pin Select (PPS) on appropriate devices.
- Supports Open-Drain Outputs capability on appropriate devices.
- Supports all interrupt modes.
- Event timing accurate to one clock period.
- Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses, stack overflow checking, etc.).
- Fully integrated in to the VSM source level debugging system.
- Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the PIC18:
- The External Memory Interface (EMI) of devices such as the PIC18F8X20 is not modelled. These devices can only be modelled when the PMx configuration bits select the Microcontroller Mode (MC) mode of operation. Specifically, the Microprocessor Mode (MP), Microprocessor with Boot Block Mode (MPBB) and Extended Microcontroller Mode (EMC) modes are not supported.
- Power Managed Modes is not modelled. Specifically, the use of IDLEN and SCS/SCSx bits in the OSCCON register to switch oscillator sources and the behaviour of the SLEEP command is not modelled. The SLEEP command always puts the processor in to full sleep mode. This limitation is largely due to poor documentation on how the power managed modes actually affect peripherals.
- Brown-out detection and High-Low Voltage Detect (HLVD) is not modelled.
- RELEASE bit effects and Brown-out wakeup from Deep Sleep mode are not modelled.
- The Internal/External Switch Over (IESO configuration bit) and the Fail Safe Clock Monitor (FSCM configuration bit) are not modelled.
- The CAN/ECAN module is not currently modelled.
- The SPP (Streaming Parallel Part) of the USB variants is not currently modelled.
- Isochronous USB transactions in the USB variants is not currently modelled.
- The external programming interface (PGC/PGD pins) are not modelled.
- The DMA features for SPI2 PGD pins are not modelled.
- The PMDx registers effects are not modelled.
- The VREGCON register effects are not modelled.
- The ACTCON register effects are not modelled.
- The SRLCON register effects are not modelled.
Compilers
Supported Third Party Compilers
Proteus VSM models will fundamentally work with the exact same HEX file as you would program the physical device with. However, far more debugging information is available when using a compiler to write the firmware and providing these object files to Proteus in place of the HEX file provides a much richer working environment.
We recommend you use the free Labcenter VSM Studio IDE. This will greatly simplify the task as it will automatically configure supported compilers to work with a Proteus VSM simulation.
If you prefer to work inside your own IDE then you will need to set your compiler options manually. After compiling for debug, all you need to do is specify the debug file from the compiler as the program property of the microcontroller on the schematic.
VSM Studio supported toolchains
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