Proteus Virtual System Modelling (VSM) combines mixed mode SPICE circuit simulation, animated components and microprocessor models to facilitate co-simulation of complete microcontroller based designs.
The ‘Proteus VSM for PIC10/12’ product includes the following main software modules:
Proteus VSM for PIC® Bundle products are ideal if you need to simulate more than one family of PIC micro-controllers.
The following is a current list of supported variants in the PIC10/12 family:
We believe our simulation models are the most accurate and the most complete on the market today. A summary of model capabilities is listed below:
- Fully simulates the entire instruction set.
- Supports all port and other I/O pin operations including weak pullup.
- Supports all timers including watchdog timer, sleep mode and wake-up from sleep.
- Supports Analogue-to-Digital Conversion (ADC) module including support for voltage reference pins.
- Supports the Analogue Comparator and Voltage Reference modules.
- Supports internal code and data EEPROM memory inc. code protection and data persistence.
- Supports all interrupt modes including pin change interrupts.
- Supports the Complementary Output Generator (CWG) module in appropriate variants.
- Supports the Configurable Logic Cell (CLC) module in appropriate variants.
- Supports the Pulse Width Modulation (PWM) module in appropriate variants.
- Supports the Numerical Controlled Oscillator (NCO) module in appropriate variants.
- Supports the Complementary Waveform Generator (CWG) module in appropriate variants.
- Internally generated processor clock for performance. Event timing accurate to one clock period.
- Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses, stack overflow checking, etc.).
- more… Fully integrated in to the VSM source level debugging system.
- more… Fully integrated into the Proteus Diagnostic Control System.
The following is a listing of known limitations in the current version of the PIC10/12:
- No significant functional limitations.
- HFINTOSC as CLC1 input is not supported for efficiency reasons.
- IVR Internal Voltage Regulator and VREGCON register effect are not modeled.
- BORCON register effect are not modeled.
Supported Third Party Compilers
Proteus VSM models will fundamentally work with the exact same HEX file as you would program the physical device with. However, far more debugging information is available when using a compiler to write the firmware and providing these object files to Proteus in place of the HEX file provides a much richer working environment.
We recommend you use the free Labcenter VSM Studio IDE. This will greatly simplify the task as it will automatically configure supported compilers to work with a Proteus VSM simulation.
If you prefer to work inside your own IDE then you will need to set your compiler options manually. After compiling for debug, all you need to do is specify the debug file from the compiler as the program property of the microcontroller on the schematic.
VSM Studio supported toolchains